The present invention relates generally to power system circuits and deals more particularly with a current balancing structure for a number of semiconductor switching devices operating in parallel.
Power converters, for example, in the 100 to 500K W range have generally been implemented through the use of thyristor semiconductor devices such as silicon controlled rectifiers (SCR). Typically the SCR's are arranged in parallel arrays and each individual SCR carries a share of the total current being switched in the power converter circuit thus providing an electrical current capacity beyond that of a single SCR. Although thyristor semiconductor devices provide substantial current handling capabilities and can withstand high voltages, such as those developed during switching in inductive circuits, they have a number of inherent disadvantages which limit power converter circuit design.
Power converter circuits employing SCR's generally require relatively complex commutation circuits to insure that the SCR's "turn-on" and "turn-off" by applying gating signals that are precisely controlled and applied for a sufficient interval to insure the build up of current through the device to a value several times the holding current of the device and accordingly, high frequency operation is limited.
Another problem associated with thyristor semiconductor devices which limits the switching frequency of a power converter circuit design with such devices is the false "turn-on" of the device when the minimum rate of rise of the forward voltage when the device is in the OFF state exceeds the rating of the device falsely causing the device to switch from the OFF state to the ON state.
The advent and availability of high power transistor devices has made it possible to design and build power converters in the 100 to 500K W range. However, the current requirements of such power converter circuits are such that a number of transistors must be operated in parallel each handling a share of the total current. The application of these high power transistor devices are limited by base drive requirements of up to 10% of the rated current and voltage breakdown limitations occuring upon "turn-on" and "turn-off".
Despite the above limitations, there are a number of advantages to utilizing high power transistor devices among which advantages are: the ability to control the switching of the devices without complex commutation circuits since the transistor device "turns-off" upon removal of the base drive, and due to the high speed switching capability, a power converter circuit is able to work at high frequencies in the 10's of Kilohertz (Khz).
Due to the high switching frequency capabilities of the high power transistors, it is now possible to build a power converter circuit using a single three phase bridge in comparison to two or more modules required when such circuits are made using thyristors or gate "turn-off" thyristor devices.
In order for the design of a single three phase bridge power converter system to be cost effective and economical, it is desirable to drive the number of parallel transistors from a single drive source. However, in order for the transistors to be driven from a single source their emitters must generally be connected together and conventional current sharing arrangements such as inserting impedances in series with the transistor cannot be used.
Furthermore, semiconductor devices, including transistors, exhibit a range of nonuniform characteristics even if fabricated from the same batch. Thus, to equalize current distribution between and through each of the parallel transistors requires that the devices be matched and which matching is a cumbersome and expensive process. In addition, it would be necessary to match replacement devices and keep these replacement devices in maintenance stock for any usage in subsequent failures.
It is known to use a current sharing network to balance the current flowing through the parallel semiconductor devices and typically balancing reactors having primary and secondary windings wound around a magnetic core are used in the power converter switching circuitry to ensure current balancing among parallel switching devices. Briefly, the magnetic flux induced in the reactor core due to current flowing in the primary and secondary windings is in opposite directions from one another so that equal currents in the primary and secondary windings cause the resulting magnetic flux produced by these currents to cancel producing zero total flux. When the currents are unequal, a non-zero total magnetic flux is induced in the windings which tends to reduce the higher current in one parallel path while raising the lower current in another parallel path thus tending to equalize the currents in their respective primary and secondary windings of the reactor in each path. Consequently, substantially equal current flows through each of the parallel semiconductor devices even though the voltage drop characteristics may be different. Reference may be made to any number of texts and reference literature known to those skilled in the art for further details of such balancing structures.
Although current balancing is possible and indeed achievable during steady state conditions, attention must be paid to the interval during which the transistors are "turned-on" or "turned-off" in response to control signals applied to the respective transistor gates. Applying the gate control signals simultaneously to all the transistors does not guarantee a simultaneous "turn-on" of all the respective transistors and likewise the removal of the control signals from each of the respective transistor gates does not ensure that the transistors will simultaneously "turn-off". Accordingly, damage or destruction of the transistors may result if the current ratings are exceeded and further if a voltage transient produced due to switching in the inductive circuit exceeds the voltage rating of the transistor devices.
Accordingly, it is a general aim of the present invention to provide a current balancing structure that provides protection for parallel transistor devices from potentially damaging high voltage transients arising during the transistor "turn-on" and "turn-off" times wherein the respective transistors may not simultaneously "turn-on" and "turn-off".
It is a further aim of the present invention to provide a current balancing structure that insures substantially equal current flow in each of the respective parallel transistors.